This invention relates generally to demodulators for digital television receivers, and more particularly to phase-lock loop units in demodulator front-ends.
The era of digital television broadcasting in the United States began officially with the introduction of terrestrial services in November, 1998. It is expected that cable and satellite digital TV broadcasting will soon become available as well. In all three transmission media, i.e., terrestrial, cable, and satellite, MPEG-2 is the common standard for video coding at the source of television signals. Because of the similarity in video coding in the three transmission media, it is possible to share signal processing functional blocks in receivers for the three media. This is the so-called multi-mode digital television receiver.
In the multi-mode digital TV receiver, the conventional approach for implementing demodulators dictates a hardware solution. This is due to the high symbol rates, i.e., 10.76 MHz for 8VSB, 5.38 MHz for 256QAM, and up to 45 MHz for QPSK. Symbols can be, for example, six or eight bits. Hardware offers computational speed not attainable by software. However, specialized hardware is very difficult to change for future upgrades, the size of the chip is large, and the cost is relatively high when compared with implementation that use software and common digital signal processors.
Therefore, it is desired to provide an alternatives to hardware implemented demodulators. These alternatives would provide flexibility, low cost, without degradation of performance while demodulating symbols at a very high rate.
The invention provides means for updating timing and error recovery blocks of a demodulator front-end of a digital television receiver. A phase-lock loop circuit in a demodulator including a timing recovery block and a carrier recovery block. The demodulator for demodulating a digital signal including symbols. The symbols are sampled at a time interval equal to or a fraction of the symbol rate. The phase-lock loop includes an integrator processing a block of N samples to produce an average of the N samples, and means for supplying the average to the timing recovery block and the carrier recovery block every NT period, where T is a sample interval. As a feature, the phase-lock loop is under software control and can operate in any one of three block-based modes as determined by a frequency offset.